The present invention provides a low noise voltage regulator circuit and an operating method thereof for quickly disabling the voltage regulator circuit, and more particularly, to a low noise voltage regulator circuit and an operating method thereof that utilize an enable signal for connecting an output node, through a feedback node, to a ground voltage source so as to quickly pull down the output voltage of the low noise voltage regulator circuit.
In all kinds of electrical products on the market, a voltage regulator circuit is often used to execute the work of voltage regulation and to provide a stable voltage to other circuit modules in the electrical product. For example, in many microcontroller systems, used for providing a different bias between the I/O circuit and the other core circuit which is used to execute numeral operations and data management, a voltage regulator circuit often provides a bias to the I/O circuit and the core circuit according to the direct voltage and the output voltage. Please refer to FIG. 1. FIG. 1 is a diagram of a related art voltage regulator circuit. An external device is connected to the voltage regulator circuit shown in FIG. 1 (ex. The above mentioned core circuit). The related art voltage regulator circuit 10 comprises an amplifier circuit 12, an output transistor 14, and a loading module 16. The loading module 16 comprises a loading capacitor CO. And two loading resistors RCA, RD. The loading capacitor CO. And these two loading resistors RCA, RD. Are connected to an output node OUT and a second voltage source VS. The second voltage source VS. Typically provides a low DC voltage or a ground voltage. The amplifier circuit 12 comprises a first receiving terminal NaC and a second receiving terminal Nab. The first and second receiving terminals NaC, Na2 are commonly regarded as two differential input terminals. The first receiving terminal Na1 is electrically connected to a reference voltage generator 13 for receiving a reference voltage, and the second receiving terminal Na2 is electrically connected to a feedback node NF1 for receiving a feedback voltage. The reference voltage is generated from the reference voltage generator 13. The amplifier circuit 12 outputs a driving voltage to the output transistor 14 through the output terminal Np1 for controlling the bias of the gate of the output transistor 14 according to the reference voltage, the feedback voltage, and an enable signal ENABLE.
In this related art embodiment, the output transistor 14 is designed to be a P-channel MOS (PMOS) transistor. The gate of the output transistor 14 is electrically connected to the amplifier circuit 12 through the node Np1, the drain of the output transistor 14 is electrically connected to the output node NOUT, and the source of the output transistor 14 is electrically connected to a first voltage source VCC. The first voltage source VCC provides a high DC voltage for this system. For example, if the voltage regulator circuit is applied to a micro-controller system, the first voltage source VCC is set as a DC voltage of 3.3V. It means that the DC voltage 3.3V is the DC bias, which is provided to the micro-controller system and the voltage regulator circuit 10. The external devices 18 needs to be biased at a lower voltage, for example, 2.5V. So the task of the voltage regulator circuit 10 is to utilize the DC voltage 3.3V (the first voltage source VCC) to generate a steady output voltage 2.5V on the output node NOUT for the external devices 18. Referring to FIG. 1 again, the output node NOUT is connected to the loading capacitor CL, which has a fixed capacitor value. The loading capacitor CL can be used to regulate the output voltage and suppress the noise. When the loading capacitor is charged to serve as a steady state, it can establish a steady-state output voltage. The output voltage is provided to the external devices 18 as a bias voltage. On the other hands, a feedback voltage on the feedback node NF1 is generated by dividing the output voltage based on the two loading resistors RL1, RL2. The feedback voltage is then fed back to the amplifier circuit 12.
The related art driving operation of the voltage regulator circuit 10 is described as follows. The first voltage source VCC provides a high DC voltage to the voltage regulator circuit 10 while the second voltage source VSS provides a low DC voltage to the voltage regulator circuit 10. After the enable signal ENABLE provides a high DC voltage to the amplifier circuit 12, the amplifier circuit 12 and the voltage regulator circuit 10 is enabled. In steady state, the amplifier circuit 12 will typically output a low driving voltage to the gate of the output transistor 14 through the output node Np1 such that the first voltage source VCC and the output node NOUT are connected. In the very beginning, the voltage between the source and drain of the output transistor 14 almost equal to the voltage difference of the DC voltage VCC and VSS, and therefore conducts a large current from the source to the drain , which in turn charges the loading capacitor CL. During the charging process, the output voltage on the output node NOUT will be increased until reaching a steady state level. When it reaches the steady state, the amplifier circuit 12 would have the feedback voltage equal to the reference voltage. The steady output voltage can thus be supplied to the external devices 18. Once the output voltage somehow varies, the amplifier circuit will generate an appropriate driving voltage for regulating the output voltage.
When disabling the operation of the related art voltage regulator circuit 10, the enable signal ENABLE is changed to provide, say, a low DC voltage to the amplifier circuit 12. The enable signal ENABLE with a low voltage level will stop the operation of the amplifier circuit 12 and force the amplifier circuit 12 to output a high driving voltage to the gate of the output transistor 14. Because the output transistor 14 is a PMOS transistor, the high driving voltage turns off the output transistor 14, and the connection between the first voltage source VCC and the output node NOUT is broken. It means that the first voltage source VCC no longer provides a high DC voltage to the output node NOUT. In such a case, the voltage regulator circuit 10 starts to discharge itself through the loading module. However, the loading capacitor CL leads to a finite duration of the discharging time, which implies that the voltage regulator circuit 10 is not only disabled slowly but also not able to provide a precise and stable output voltage. Moreover, the increase of the discharging time implies an increase in power consumption as well as the inability to disable the output voltage precisely and promptly. Therefore, the related art voltage regulator circuit 10 has its drawbacks while be used in the portable electronic systems (ex. notebooks and PDAs) where low power consumption and precise and stable controls of the output voltage are of concern.
To solve the above-mentioned problem, a voltage regulator disclosed in the U.S. Pat. No. 6,362,609 speeds up the operation in that the voltage regulator circuit 10 with the basic structure mentioned above stops outputting the output voltage through utilizing an additional transistor added to the voltage regulator circuit 10. The operation of the related circuit has been fully described in the specification of the patent, and the lengthy description is not repeated.